1. Field of the Invention
This invention relates to semiconductor device metrology, and more particularly, a method for preparing samples for TEM analysis.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabricating a microelectronic device with one or more parameters outside the design specifications of the device may hinder or prohibit the function of the device, leading to a reduction in production efficiency and device quality. Consequently, the fabrication of microelectronic devices often includes analyzing microelectronic topographies at different stages of the process to insure that the devices formed therefrom meet their specified functionality requirements. In fact, as production volumes and efforts to improve process control increase in the integrated circuit fabrication industry, the ability to accurately analyze microelectronic processes and the materials associated with such processes in a timely manner becomes more critical. In general, the term “microelectronic topography,” as used herein, may refer to a semiconductor substrate having one or more layers formed thereon, regardless of whether a functioning device has been formed from the topography or not. As such, the term “microelectronic topography” may generally refer to a structure used to fabricate a microelectronic device at any given point in the fabrication process. In addition, the “analysis of a microelectronic topography,” as used herein, is not restricted solely to analyzing the upper surface of a wafer, but may include analyzing more than one layer and/or the substrate of the topography.
A microelectronic topography may be analyzed for a number of different properties. For example, a microelectronic topography may be analyzed for its electrical properties, composition, and/or physical thickness of individual layers and/or structures, to name just a few. Consequently, a number of different techniques may be used to analyze a microelectronic topography. For example, transmission electron microscopy cross-sectional analysis (hereinafter referred to as “TEM”) may be used to analyze a microelectronic topography. TEM generally involves directing an electron beam at a microelectronic topography while a photograph is simultaneously taken. Both the photograph and electron beam are used to analyze the exposed layers.
There are a few different manners with which to prepare the sample of the microelectronic topography for TEM analysis. One manner is referred to herein as the “wedge method.” The wedge method involves dicing a wafer into small fragments and polishing two opposing cross-sectional sides of a fragment to a target location. Subsequently, a portion of the polished fragment is etched to form an image region having a thickness of a few thousands angstroms and a large viewing area with which to analyze. Such a process generally offers a good image quality, but is very labor intensive. In particular the polishing process is an intricate and time-consuming process, requiring a highly skillful person to manually polish the sample against a variety of different polishing pads and frequently check whether the target location has been obtained. In addition to obtaining the target location, the polishing processes are used to form the fragment into a wedge-shape such that one end is thicker than an opposing end of the fragment. Although the formation of the wedge-shape provides some support, a sample prepared using this technique is still susceptible to breaking. Furthermore, the wedge method involves dicing an entire wafer into multiple fragments. As a result, the wafer cannot be used for purposes that involve a whole wafer.
Another technique for preparing TEM samples is referred to herein as the “FIB lift out method.” The FIB lift out method involves using a relatively high energy focused ion beam to cut a fragment out of a wafer which is generally significantly smaller than the fragment cut out in the wedge method. In particular, the cutting technique employed by the FIB lift out method offers a manner in which to more precisely locate the target location of the wafer and, therefore, does not require the entire wafer to be diced. Consequently, the wafer may be used for other processing or samples. Moreover, the fragment cut out by the FIB lift out method typically only includes a portion of substrate and, therefore, is thinner than the fragment cut out in the wedge method. The thinner fragment is subsequently lifted from the wafer and immediately transferred to a carbon coated copper grid for analysis. In this manner, the FIB lift out method is significantly faster than the wedge method. On the other hand, however, the FIB lift out method does not allow further thinning of the sample to be conducted. In addition, the FIB lift out method causes significant damage to the crystalline structure of the substrate and generally does not produce a quality image or a large viewing area. Moreover, the FIB lift out method redeposits materials along the sidewalls of samples.
It would, therefore, be desirable to develop a method of preparing TEM samples that overcomes the aforementioned problems. In particular, it would be beneficial to form a TEM sample having good image quality without having a thick damaged crystalline structure or a thick redeposited layer. In addition, it would be advantageous to be able to perform energy dispersive spectroscopy (EDS) analysis without the artifact of carbon film. Moreover, it would be beneficial to develop a method for preparing TEM samples in which the thickness of the sample can be thinned for multiple analyses. Furthermore, it would be particularly advantageous for such a method to be fast and uncomplicated.